1. Field of the Invention
This invention relates to semiconductor device fabrication methods and, more particularly, to a CMOS and bipolar fabrication process using selective epitaxial growth.
2. Description of the Related Art
As device geometries get smaller, well tried technologies become inadequate for isolating devices of the same or opposite conductivity type. For example, the widely used LOCOS (isoplanar) scheme requires too much silicon area for geometries below one micron, due to the bird's beak encroachment. In addition, latch-up considerations in CMOS prevent putting opposite type devices in very close proximity unless more complex processing is added.
Current state-of-the-art one to two micron level approaches to CMOS isolation include the use of trenches and epitaxial buried layers. Trench isolation has the disadvantage of requiring very complex and costly processing, and it requires some other type of oxide isolation for the majority of the chip's surface (typically LOCOS). Additionally. MOS transistors cannot be set directly against a trench wall because of degradation of device characteristics, thus increasing the area consumed by one transistor. Epitaxial buried layer isolation, while somewhat effective, still has a lower limit of approximately 2.5 micrometers for PMOS to NMOS spacing due to junction breakdown and punch-through.
Recently. CMOS isolation by selective epitaxial growth (SEG) has been proposed. In one method, not necessarily in the prior art, a silicon substrate is etched to form openings in the substrate, and insulators are formed on the side walls of the openings. Thereafter, the substrate is masked and doped to a chosen conductivity type, and an epitaxial layer is grown to fill the openings. A final LOCOS isolation then is performed. The disadvantages of this method are the requirement of etching into the silicon surface and the requirement of LOCOS isolation with the inherent bird's beak encroachment.
In another technique, also not necessarily in the prior art, a silicon dioxide layer is formed over a silicon substrate, and the silicon dioxide layer is etched for forming openings extending to the substrate. The openings are filled by growing epitaxial layers having a selected conductivity type (e.g., N-type) on the substrate. This creates doped wells in which devices of a particular type may be constructed. The wells then are covered by thin thermal oxide layers to protect them from later process steps. The process then is repeated to form wells having an opposite conductivity type (e.g., P-type). Thereafter, the thin oxide layers over the previously formed wells are stripped. Although this method does not require LOCOS isolation, it must be implemented with multiple SEG steps.